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cy7c1381d cy7c1383d cy7c1383f 18-mbit (512 k 36/1 m 18) flow-through sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05544 rev. *r revised october 8, 2013 618-mbit (512 k 36/1 m 18) flow through sram features supports 133 mhz bus operations 512 k 36 and 1 m 18 common i/o 3.3 v core power supply (v dd ) 2.5 v or 3.3 v i/o supply (v ddq ) fast clock-to-output time ? 6.5 ns (133 mhz version) provides high performance 2-1-1-1 access rate user selectable burst counter supporting intel pentium interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed write asynchronous output enable cy7c1381d available in jedec-standard pb-free 100-pin tqfp, pb-free and non pb-free 165-ball fbga package. cy7c1383d available in jedec-standard pb-free 100-pin tqfp. cy7c1383f available in non pb-free 165-ball fbga package. ieee 1149.1 jtag-compatible boundary scan zz sleep mode option functional description the cy7c1381d/cy7c1383d/cy7c1383f is a 3.3 v, 512 k 36 and 1 m 18 synchronous flow through srams, designed to interface with high speed microprocessors with minimum glue logic. maximum a ccess delay from clock rise is 6.5 ns (133 mhz version). a 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. all synchronous inputs are gated by registers controlled by a positive edge triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. the cy7c1381d/cy7c1383d/cy7c1383f allows interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses ca n be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). cy7c1381d/cy7c1383d/cy7c1383f operates from a +3.3 v core power supply while all outputs operate with a +2.5 v or +3.3 v supply. all inputs and outputs are jedec-standard and jesd8-5-compatible. selection guide description 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma errata: for information on silicon errata, see ?errata? on page 32. details include trigger conditions, devices affected, and proposed workaround.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 2 of 37 logic block diagram ? cy7c1381d (512 k 36) [1] address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] dqs dqp a dqp b dqp c dqp d a0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep dq a , dqp a byte write register dq b , dqp b write register dq c , dqp c write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c write register dq b , dqp b write register dq a , dqp byte write register logic block diagram ? cy7c1383d/cy7c1383f (1 m 18) [1] address register adv burst counter and q1 q0 ce 1 oe sense amps memory array output buffers input registers mode ce 2 ce 3 gw bwe a0,a1,a bw b bw a dq b ,dqp b dq a ,dqp a enable a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control note 1. cy7c1383f have only 1 chip enable (ce 1 ).
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 3 of 37 contents pin configurations ........................................................... 4 pin definitions .................................................................. 6 functional overview ........................................................ 8 single read accesses ................................................ 8 single write accesse s initiated by adsp ................... 8 single write accesses initiate d by adsc ................... 8 burst sequences ......................................................... 8 sleep mode ................................................................. 8 interleaved burst address tabl e ................................. 9 linear burst address table ......................................... 9 zz mode electrical characteri stics .............................. 9 truth table ...................................................................... 10 truth table for read/write ............................................ 11 truth table for read/write ............................................ 11 ieee 1149.1 serial boundary sc an (jtag [14] ) ........... 12 disabling the jtag feature ...................................... 12 test access port (tap) ............................................. 12 performing a tap r eset .......... .............. .......... 12 tap registers ...................................................... 12 tap instruction set ................................................... 13 tap controller state diagram ....................................... 14 tap controller block diagram ...................................... 15 tap timing ...................................................................... 16 tap ac switching characteristics ............................... 16 3.3 v tap ac test conditions ....................................... 17 3.3 v tap ac output load equivalent ......................... 17 2.5 v tap ac test conditions ....................................... 17 2.5 v tap ac output load equivalent ......................... 17 tap dc electrical characteristics and operating conditions ..................................................... 17 identification register definitions ................................ 18 scan register sizes ....................................................... 18 instruction codes ........................................................... 18 boundary scan order .................................................... 19 maximum ratings ........................................................... 20 operating range ............................................................. 20 neutron soft error immunity ......................................... 20 electrical characteristics ............................................... 20 capacitance .................................................................... 21 thermal resistance ........................................................ 21 ac test loads and waveforms ..................................... 22 switching characteristics .............................................. 23 timing diagrams ............................................................ 24 ordering information ...................................................... 28 ordering code definitions ..... .................................... 28 package diagrams .......................................................... 29 acronyms ........................................................................ 31 document conventions ................................................. 31 units of measure ....................................................... 31 errata ............................................................................... 32 part numbers affected .............................................. 32 product status ........................................................... 32 ram9 sync zz pin & jtag issues errata summary ..................... .......................................... 32 document history page ................................................. 34 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc? solutions ...................................................... 37 cypress developer community ................................. 37 technical support ................. .................................... 37
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 4 of 37 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout (3 chip enable) [2] a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1381d (512 k 36) v ss /dnu a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1383d (1 m 18) v ss /dnu a a note 2. errata: the zz pin (pin 64) needs to be externally co nnected to ground. for more information, see ?errata? on page 32.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 5 of 37 figure 2. 165-ball fbga (13 15 1.4 mm) pinout (3 chip enable) [3, 4] pin configurations (continued) cy7c1381d (512 k 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1383f (1 m 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b v ss dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc nc/36m nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a notes 3. errata: the zz ball (h11) needs to be externally connected to ground. for more information, see ?errata? on page 32. 4. errata: the jtag testing should be performed with these devices in bypass mode as the jtag functionality is not guaranteed. for more in formation, see ?errata? on page 32.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 6 of 37 pin definitions name i/o description a 0 , a 1 , a input synchronous address inputs used to select one of the address location s. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the 2-bit counter. bw a , bw b , bw c , bw d input synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). clk input clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input synchronous advance input signal. sampled on the rising edge of clk. when asserted, it auto matically increments the address in a burst cycle. adsp input synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe input synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz [5] input asynchronous zz sleep input . this active high input places the device in a non time critical sleep condition with data integrity preserved. for normal operation, this pin ha s to be low or left floating. zz pin has an internal pull down. dq s i/o synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins b ehave as outputs. when high, dq s and dqp x are placed in a tristate condition.the outputs are automatically tristated during t he data portion of a write sequence, during the first clock when emerging from a desel ected state, and when t he device is deselected, regardless of the state of oe . dqp x i/o synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. note 5. errata: the zz pin needs to be externally connected to ground. for more information, see ?errata? on page 32.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 7 of 37 mode input static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull-up. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . tdo [6] jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being used, this pin can be left unconnected. this pin is not available on tqfp packages. tdi [6] jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feat ure is not being used, this pin can be left floating or connected to v dd through a pull-up resistor. this pin is not available on tqfp packages. tms [6] jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feat ure is not being used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck [6] jtag clock clock input to th e jtag circuitry . if the jtag feature is not being us ed, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die. 36 m, 72m, 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. v ss /dnu ground/dnu this pin can be connected to ground or can be left floating. pin definitions (continued) name i/o description note 6. errata: the jtag testing should be performed with these devices in bypass mode as the jtag functionality is not guaranteed. for more in formation, see ?errata? on page 32.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 8 of 37 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133 mhz device). cy7c1381d/cy7c1383d/cy7c1383f supports secondary cache in systems using a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 processors. the linear burst sequence is suited for processors that use a linear burst sequenc e. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for t he rest of the burst access. byte write operations are qualified with the byte write enable (bw e ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplif ied with on-chip synchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address regist er and the burst counter and/or control logic, and later presented to the memory core. if the oe input is asserted low, the requested data is available at the data outputs with a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs (gw , bw e , and bw x ) are ignored during this fi rst clock cycle. if the write inputs are asserted active (see truth table for read/write on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. byte writes are allowed. all i/o are tristated during a byte write. as this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/o must be tristated prior to the presentation of data to dqs. as a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw x ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core the in formation presented to dq [a:d] is written into the specified address location. byte writes are allowed. all i/o are tristated when a write is detected, even a byte write. because this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/o must be tristated prior to the presentation of data to dq s . as a safety precaution, the data lines are tristated when a write cycle is detected, regardless of the state of oe . burst sequences cy7c1381d/cy7c1383d/cy7c1383f provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode selects a linear burst sequence. a high on mode sele cts an interleaved burst order. leaving mode unconnected causes the device to default to a interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conserva tion sleep mode. two clock cycles are required to enter into or exit from this sleep mode. while in this mode, data integrity is guaranteed. accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the sleep mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 9 of 37 interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 80 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 10 of 37 truth table the truth table for cy7c1381d/cy7c1383d/cy7c1383f follows. [7, 8, 9, 10, 11] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power down none h x x l x l x x x l?h tri-state deselected cycle, power down none l l x l l x x x x l?h tri-state deselected cycle, power down none l x h l l x x x x l?h tri-state deselected cycle, power down none l l x l h l x x x l?h tri-state deselected cycle, power down none x x x l h l x x x l?h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 7. x = don't care, h = logic high, l = logic low. 8. write = l when any one or more byte write enable signals, and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 9. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 10. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tristate. oe is a don't care for the remainder of the write cycle. 11. oe is asynchronous and is not sampled with t he clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 11 of 37 truth table for read/write the truth table for cy7c1381d read/write follows. [12, 13] function (cy7c1381d) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a (dq a , dqp a )hlhhhl write byte b(dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )hlhhll write byte c (dq c , dqp c )hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a )hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )hlhllh write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a ) hlhlll write byte d (dq d , dqp d )hllhhh write bytes d, a (dq d , dq a, dqp d , dqp a )hllhhl write bytes d, b (dq d , dq a, dqp d , dqp a )hllhlh write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllhll write bytes d, b (dq d , dq b, dqp d , dqp b ) hlllhh write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a ) hlllhl truth table for read/write the truth table for cy7c1383d/cy7c1383f read/write follows. [12, 13] function (cy7c1383d/cy7c1383f) gw bwe bw b bw a write bytes d, c, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hl l l write all bytes h l l l write all bytes l x x x read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x notes 12. x=don't care, h = logic high, l = logic low. 13. the table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is done bas ed on which byte write is active.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 12 of 37 ieee 1149.1 serial boundary scan (jtag [14] ) the cy7c1381d/cy7c1383f incorporates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. cy7c1381d/cy7c1383f contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo may be left unconnected. at power up, the device comes up in a reset state, which does not inte rfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 14 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes on page 18 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected betw een the tdi and tdo balls and allow data to be scanned in and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 15 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 19 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 18 . note 14. errata: the jtag testing should be performed with t hese devices in bypass mode as the jtag functionality is not guaranteed. for more in formation, see ?errata? on page 32.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 13 of 37 tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in instruction codes on page 18 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state, when the instruction re gister is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction when it is shifte d in, the tap controller needs to be moved into the update-ir state. extest the extest instruction enables the preloaded data to be driven out through the system output pins . this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. the sample z command places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data is shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #89 (for 165-ball fbga package). wh en this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the outp ut (q-bus) pins, when the extest is entered as the current instru ction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is power ed up, and also when the tap controller is in the te st-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 14 of 37 tap controller state diagram the 0 or 1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 15 of 37 tap controller block diagram bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck tms tap controller tdi tdo
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 16 of 37 tap timing figure 3. tap timing t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined tap ac switchi ng characteristics over the operating range parameter [15, 16] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 15. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 16. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 17 of 37 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 2.5 v tap ac output load equivalent tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 3.3 v 0.165 v unless otherwise noted) parameter [17] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 8.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 17. all voltages referenced to v ss (gnd).
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 18 of 37 identification regi ster definitions instruction field cy7c1381d (512 k 36) cy7c1383f (1 m 18) description revision number (31:29) 000 000 describes the version number. device depth (28:24) [18] 01011 01011 reserved for internal use. device width (23:18) 165-ball fbga 000001 000001 defines the memory type and architecture. cypress device id (17:12) 100101 010101 defines the width and density. cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size ( 36) bit size ( 18) instruction bypass 3 3 bypass 11 id 32 32 boundary scan order (165-ball fbga package) 89 89 instruction codes instruction code description extest 000 captures input/output ring contents. pl aces the boundary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id register wit h the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures input/output ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use. this instruct ion is reserved for future use. sample/preload 100 captures input/ou tput ring contents. places the boun dary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use. this instruct ion is reserved for future use. reserved 110 do not use. this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. note 18. bit #24 is ?1? in the register definitions for both 2.5 v and 3.3 v versions of this device.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 19 of 37 boundary scan order 165-ball fbga [19, 20] bit # ball id bit # ball id bit # ball id 1n6 31d10 61g1 2n7 32c11 62d2 3n10 33a11 63e2 4p11 34b11 64f2 5p8 35a10 65g2 6r8 36b10 66h1 7r9 37a9 67h3 8p938b968j1 9p10 39c10 69k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13n11 43b7 73k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18m10 48a4 78p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21j10 51a3 81p3 22 h9 52 a2 82 r3 23h10 53b2 83p2 24 g11 54 c2 84 r4 25f11 55b1 85p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28 g10 58 d1 88 r6 29 f10 59 e1 89 internal 30 e10 60 f1 notes 19. balls which are nc (no connect) are pre-set low. 20. bit# 89 is pre-set high.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 20 of 37 maximum ratings exceeding the maximum ratings may impair the useful life of the device. for user guidelines, not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .....?0.3 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.3 v to +v dd dc voltage applied to outputs in tri-state ........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) ...... .................................. 20 ma static discharge voltage (per mil-std-883, method 3015) .......................... > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max [21] unit lsbu logical single-bit upsets 25 c 361 394 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev electrical characteristics over the operating range parameter [22, 23] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [22] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [22] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v dd, output disabled ?5 5 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5 ns cycle, 133 mhz ?210ma 10 ns cycle, 100 mhz ? 175 ma notes 21. no lmbu or sel events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. fo r more details refer to application note an54908, accelerated neutron ser testing and calculation of terrestrial failure rates . 22. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 23. t power up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 21 of 37 i sb1 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = f max , inputs switching 7.5 ns cycle, 133 mhz ?140ma 10 ns cycle, 100 mhz ? 120 i sb2 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 70 ma i sb3 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? v ddq ? 0.3 v or v in ? 0.3 v, f = f max , inputs switching 7.5 ns cycle, 133 mhz ?130ma 10 ns cycle, 100 mhz ? 110 i sb4 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 80 ma electrical characteristics (continued) over the operating range parameter [22, 23] description test conditions min max unit capacitance parameter [24] description test conditions 100-pin tqfp package 165-ball fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 59pf c clk clock input capacitance 5 9 pf c io input/output capacitance 5 9 pf thermal resistance parameter [24] description test conditions 100-pin tqfp package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.66 20.7 c/w ? jc thermal resistance (junction to case) 4.08 4.0 c/w note 24. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 22 of 37 ac test loads and waveforms figure 4. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 23 of 37 switching characteristics over the operating range parameter [25, 26] description 133 mhz 100 mhz unit min max min max t power v dd (typical) to the first access [27] 1 ?1? ms clock t cyc clock cycle time 7.5 ?10? ns t ch clock high 2.1 ?2.5? ns t cl clock low 2.1 ?2.5? ns output times t cdv data output valid after clk rise ? 6.5 ? 8.5 ns t doh data output hold after clk rise 2.0 ?2.0? ns t clz clock to low z [28, 29, 30] 2.0 ? 2.0 ? ns t chz clock to high z [28, 29, 30] 0 4.0 0 5.0 ns t oev oe low to output valid ? 3.2 ? 3.8 ns t oelz oe low to output low z [28, 29, 30] 0 ? 0 ? ns t oehz oe high to output high z [28, 29, 30] ? 4.0 ? 5.0 ns setup times t as address setup before clk rise 1.5 ?1.5? ns t ads adsp , adsc setup before clk rise 1.5 ?1.5? ns t advs adv setup before clk rise 1.5 ?1.5? ns t wes gw , bwe , bw [a:d] setup before clk rise 1.5 ?1.5? ns t ds data input setup before clk rise 1.5 ?1.5? ns t ces chip enable setup 1.5 ?1.5? ns hold times t ah address hold after clk rise 0.5 ?0.5? ns t adh adsp , adsc hold after clk rise 0.5 ?0.5? ns t weh gw , bwe , bw [a:d] hold after clk rise 0.5 ?0.5? ns t advh adv hold after clk rise 0.5 ?0.5? ns t dh data input hold after clk rise 0.5 ?0.5? ns t ceh chip enable hold after clk rise 0.5 ?0.5? ns notes 25. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 26. test conditions shown in (a) of figure 4 on page 22 unless otherwise noted. 27. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially, before a read or write operation can be initiated. 28. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 4 on page 22 . transition is measured 200 mv from steady-state voltage 29. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention conditi on, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system condition. 30. this parameter is sampled and not 100% tested.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 24 of 37 timing diagrams figure 5. read cycle timing [31] t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle dont care undefined adsp adsc gw, bwe,bw x ce adv oe note 31. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 25 of 37 figure 6. write cycle timing [32, 33] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for ?rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) data out (q) notes 32. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 33. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 26 of 37 figure 7. read/write cycle timing [34, 35, 36] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes dont care undefined adsp adsc bwe, bw x ce adv oe data in (d) data out (q) notes 34. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 35. the data bus (q) remains in high z following a write cycle, unless a new read ac cess is initiated by adsp or adsc . 36. gw is high.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 27 of 37 figure 8. zz mode timing [37, 38] timing diagrams (continued) t zz i supply clk zz t zzrec all inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 37. device must be deselected when entering zz mode. see truth table on page 10 for all possible signal conditions to deselect the device. 38. dqs are in high z when exiting zz sleep mode.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 28 of 37 ordering information cypress offers other versions of this type of product in many different configurations an d features. the below table contains o nly the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales re presentative. cypress maintains a worldwide network of offices, solution centers, manufacturer's r epresentatives and distributors. to find the office closest to you, visit us at t http://www.cypress.com/go/datasheet/offices . ordering code definitions speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1381d-133axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1383d-133axc cy7c1381d-133axi lndustrial cy7c1383d-133axi cy7c1383f-133bzi 51-85180 165-bal l fbga (13 15 1.4 mm) 100 cy7c1381d-100axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1381d-100bzi 51-85180 165-ball fb ga (13 15 1.4 mm) lndustrial cy7c1381d-100bzxi 165-ball fbga (13 15 1.4 mm) pb-free temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz a = 100-pin tqfp bz = 165-ball fbga frequency range: xxx = 133 mhz or 100 mhz die revision: x = d or f d ? 90 nm f ? errata fix pcn084636 part identifier: 138x = 1381 or 1383 1381 = ft, 512 kb 36 (18 mb) 1383 = ft, 1 mb 36 (18 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress x cy 138x x - xxx xx c 7 x
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 29 of 37 package diagrams figure 9. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 30 of 37 figure 10. 165-ball fbga (13 15 1.4 mm) bb165d /bw165d (0.5 ball diameter) package outline, 51-85180 package diagrams (continued) 51-85180 *f
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 31 of 37 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lmbu logical multi-bit upsets lsb least significant bit lsbu logical single-bit upsets msb most significant bit oe output enable sel single event latch up sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 32 of 37 errata this section describes the ram9 sync zz pin and jtag issues. de tails include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. please contact your local cypress sales representative if you have further quest ions. part numbers affected product status all of the devices in the ram9 18mb sync family are qualified and available in production quantities. ram9 sync zz pin & jtag issues errata summary the following table defines the errata applicable to available ram9 18mb sync family devices. density & revision package type operating range 18mb-ram9 synchronous srams: cy7c138*d, cy7c138*f 100-pin tqfp commercial/ industrial 165-ball fbga industrial item issues description device fix status 1. zz pin when asserted high, the zz pin places device in a ?sleep? condition with data integrity preserved.the zz pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 18m-ram9 (90 nm) for the 18m ram9 (90 nm) devices, there is no plan to fix this issue. 2. jtag functionality during jtag test mode, the boundary scan circuitry does not perform as described in the datasheet.however, it is possible to perform the jtag test with t hese devices in ?bypass mode?. 18m-ram9 (90 nm) this issue will be fixed in the new revision, which use the 65 nm technology. please contact your local sales rep for availability.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 33 of 37 1. zz pin issue problem definition the problem occurs only when the device is operated in the no rmal mode with zz pin left floating. the zz pin on the sram device does not have an internal pull-do wn resistor. switching noise in the system may cause the sram to recognize a high on the zz input, which may cause the sram to enter sleep mode. this could result in incorrect or undesirable operation of the sram. trigger conditions device operated with zz pin left floating. scope of impact when the zz pin is left floating, the device delivers incorrect data. workaround tie the zz pin externally to ground. fix status for the 18m ram9 (90 nm) devices, there is no plan to fix this issue. 2. jtag functionality problem definition the problem occurs only when the device is operated in the jt ag test mode.during this mode , the jtag circuitry can perform incorrectly by delivering the incorrect data or the incorrect scan chain length. trigger conditions several conditions can trigger this failure mode. 1. the device can deliver an incorrect lengt h scan chain when operating in jtag mode. 2. some byte write inputs only recognize a logic high level when in jtag mode. 3. incorrect jtag data can be read from the device wh en the zz input is tied high during jtag operation. scope of impact the device fails for jtag tes t. this does not impact the normal functionality of the device. workaround 1.perform jtag testing with t hese devices in ?bypass mode?. 2.do not use jtag test. fix status this issue will be fixed in the new revision, which use the 65 nm technology. please contact your local sales rep for availabili ty.
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 34 of 37 document history page document title: cy7c1381d/cy7c1383d/cy7c1383f, 18-mbit (512 k 36/1 m 18) flow-through sram document number: 38-05544 rev. ecn no. orig. of change submission date description of change ** 254518 rkf see ecn new data sheet *a 288531 syt see ecn updated features (removed 117 mhz speed bin). updated selection guide (removed 117 mhz speed bin). updated ieee 1149.1 serial boun dary scan (jtag [14]) (edited description for non-compliance with 1149.1) updated electrical characteristics (removed 117 mhz speed bin). updated switching characteristics (removed 117 mhz speed bin). updated ordering information (added pb-free information for 100-pin tqfp, 119-ball bga and 165-ball fbga package) and added comment of ?pb-free bg packages availability? below the ordering information. *b 326078 pci see ecn changed status from preliminary to final. updated pin configurations (address expansion pins/balls in the pinouts for all packages are modified as per jedec standard). updated tap instruction set (changed description of overview and extest sub-sections, added a sub-section extest output bus tri-state ). updated identification register definitions (splitted device width (23:18) row into two rows device width (23:18) 119-ball bga and another row device width (23:18) 165-ball fbga). updated electrical characteristics (modified test conditions for v ol, v oh parameters). updated thermal resistance (changed ? ja for 100-pin tqfp package from 31 ? c/w to 28.66 ? c/w, changed ? jc for 100-pin tqfp package from 6 ? c/w to 4.08 ? c/w, changed ? ja for 119-ball bga package from 45 ? c/w to 23.8 ? c/w, changed ? jc for 119-ball bga package from 7 ? c/w to 6.2 ? c/w, changed ? ja for 165-ball fbga package from 46 ? c/w to 20.7 ? c/w, changed ? jc for 165-ball fbga package from 3 ? c/w to 4.0 ? c/w). updated ordering information (updated part numbers) and removed comment of ?pb-free bg packages availab ility? below the ordering information. *c 351895 pci see ecn updated ordering information (updated part numbers). *d 416321 nxr see ecn changed address of cypre ss semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? updated electrical characteristics (changed description of i x parameter from input load current to i nput leakage current, changed the minimum value of i x parameter corresponding to input current of mode from ?5 ? a to ?30 ? a, changed the maximum value of i x parameter corresponding to input current of mode from 30 ? a to 5 ? a, changed the minimum value of i x parameter corresponding to input current of zz from ?30 ? a to ?5 ? a, changed the minimum value of i x parameter corresponding to input current of zz from 5 ? a to 30 ? a, changed v ih < v dd to v ih < v dd in note 23 ). updated ordering information (updated part numbers) and replaced package name column with package diagram in the ordering information table. *e 475009 vkn see ecn updated tap ac switching characteristics (changed the minimum values of t th , t tl parameters from 25 ns to 20 ns and changed the maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *f 776456 vkn see ecn added part numbers cy7c1381f and cy7c1383f and its related information. added note 1 regarding chip enable. updated ordering information (updated part numbers).
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 35 of 37 *g 2752731 vkn / pyrs 08/17/09 added neutron soft error immunity . updated ordering information (by including parts that are available) and modified the disclaimer for the ordering information. *h 2897182 njy 03/22/2010 updated ordering information (removed inactive parts). updated package diagrams . *i 3159479 njy 02/01/2011 updated package diagrams . added acronyms and units of measure . minor edits and updated in new template. *j 3192403 njy 03/10/2011 updated in new template. *k 3210400 njy 03/30/2011 updated ordering information (removed pruned part cy7c1381f-133bgc). *l 3440174 njy 11/16/2011 updated ordering information (added two part numbers cy7c1383d-133axc and cy7c1383d-133axi). *m 3489571 njy 01/10/2012 updated ordering information (added part number cy7c1383f-133bzi). updated package diagrams . *n 3578427 prit 04/11/2012 updated features (removed cy7c1381f related information, removed 119-ball bga package related information, removed 165-ball fbga package related information for cy7c1383d, added 165-ball fbga package related information for cy7c1383f). updated functional description (removed cy7c1381f related information, removed the note ?for best practices or recommendations, refer to the cypress application note an1064, sram system design guidelines on www.cypress.com .? and its reference, removed the note ?ce 3, ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in 1 chip enable.?). updated logic block diagram ? cy7c1381d (removed cy7c1381f related information). updated pin configurations (removed cy7c1381f related information, removed 119-ball bga package related information, removed 165-ball fbga package related information for cy7c1383d, added 165-ball fbga package related information for cy7c1383f). updated pin definitions (removed the note ?ce 3, ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in 1 chip enable.? and its reference). updated functional overview (removed cy7c1381f related information, removed the note ?ce 3, ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in 1 chip enable.? and its reference). updated truth table (removed cy7c1381f related information). updated truth table for read/write (removed cy7c1381f related information). updated ieee 1149.1 serial boun dary scan (jtag [14]) (removed cy7c1381f and cy7c1383d related information). updated identification register definitions (removed cy7c1381f and cy7c1383d related information, removed 119-ball bga package related information). updated scan register sizes (removed 119-ball bga package related information). removed boundary scan order (corresponding to 119-ball bga package). updated capacitance (removed 119-ball bga package related information). updated thermal resistance (removed 119-ball bga package related information). updated package diagrams (removed 119-ball bga package related information). document history page (continued) document title: cy7c1381d/cy7c1383d/cy7c1383f, 18-mbit (512 k 36/1 m 18) flow-through sram document number: 38-05544 rev. ecn no. orig. of change submission date description of change
cy7c1381d cy7c1383d cy7c1383f document number: 38-05544 rev. *r page 36 of 37 *o 3945784 prit 03/27/2013 updated package diagrams : spec 51-85180 ? changed revision from *e to *f. *p 3977530 prit 04/22/2013 added errata . *q 4068739 prit 07/20/2013 added errata foot notes (note 2, 3, 4, 5, 6, 14). updated pin configurations : added note 2 and referred the same note in figure 1 . added note 3, 4 and referred the same note in figure 2 . updated pin definitions : added note 5 and referred the same note in zz pin. added note 6 and referred the same note in tdo, tdi, tms, tck pins. updated ieee 1149.1 serial boun dary scan (jtag [14]) : added note 14 and referred the same note in jtag in the heading. updated errata . updated in new template. *r 4150971 prit 10/08/2013 updated errata . document history page (continued) document title: cy7c1381d/cy7c1383d/cy7c1383f, 18-mbit (512 k 36/1 m 18) flow-through sram document number: 38-05544 rev. ecn no. orig. of change submission date description of change
document number: 38-05544 rev. *r revised october 8, 2013 page 37 of 37 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1381d cy7c1383d cy7c1383f ? cypress semiconductor corporation, 2004-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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